dorsaVi has completed the design of its first integrated RRAM-CMOS validation chip, featuring self-checking write-and-verify, compute-in-memory capabilities, and scalable integration on commercial CMOS wafers. The milestone sets the stage for fabrication and commercial engagement in high-value edge AI markets.
- RRAM-CMOS validation chip design finalized, ready for fabrication
- Self-checking write-and-verify circuitry enhances memory reliability
- Compute-in-memory macros reduce power and latency for edge AI
- Back-end-of-line integration enables scalable manufacturing on TSMC wafers
- Targets exoskeletons, defence, robotics, and industrial AI applications
Milestone Reached with Chip Design Lock-In
dorsaVi Limited (ASX:DVL) has reached a pivotal point in its ultra-edge intelligence ambitions by finalising the design package for its first integrated resistive RAM (RRAM) and CMOS validation chip. Developed alongside NTU Singapore and ITRI Taiwan, this design now moves to tape-out and fabrication, marking a transition from concept to silicon. The chip aims to validate key architectural features that underpin dorsaVi’s strategy to embed AI-driven decision-making directly on devices without cloud reliance.
Write-and-Verify Circuitry Tackles RRAM Variability
RRAM technology stores data through resistance states, but variability in programming these states can erode memory reliability. dorsaVi’s chip incorporates a self-checking write-and-verify circuit that reads back each memory cell’s state immediately after programming, ensuring it falls within an acceptable resistance window. This closed-loop approach reduces marginal write errors, strengthens sensing margins, and provides valuable silicon-level data to optimise future memory reliability and yield. Such robustness is critical for demanding applications like defence, medical devices, and robotics, where stable local memory operation is non-negotiable.
Compute-in-Memory Cuts Power and Latency in Edge AI
One of the chip’s standout innovations is its compute-in-memory (CIM) capability. Unlike traditional architectures that shuttle data back and forth between memory and processors, an energy-intensive bottleneck, dorsaVi’s design enables the same RRAM array to perform local accumulation across up to 64 inputs. This dual-mode operation, switching between binary memory and compute modes, promises to reduce power consumption and speed up decision-making in edge AI scenarios. The architecture aligns with neuromorphic computing trends, aiming to deliver intelligence where data is captured, critical for applications with tight energy budgets.
Back-End-of-Line Integration Supports Commercial Scale
dorsaVi’s RRAM stack is integrated into the chip’s back-end-of-line (BEOL) metal layers, layered atop standard commercial CMOS front-end wafers sourced from TSMC. This approach avoids altering transistor-level processes, enabling the chip to leverage existing foundry lines and scale production efficiently. BEOL-compatible integration is a practical pathway to higher memory densities and compact memory-compute architectures, essential for future node migration and manufacturability. The design’s commercial CMOS foundation reflects a pragmatic route to market-ready ultra-edge hardware.
Focused on High-Value Edge Markets
The chip targets sectors where local, low-power, non-volatile intelligence is crucial. Smart exoskeletons, for instance, require fast, reliable memory to process muscle signals and user intent in real time. Robotics applications benefit from calibrated joint controllers that retain settings through power cycles. Industrial AI demands on-device models with non-volatile weights to avoid power-hungry reloads. dorsaVi’s validation chip aims to underpin these markets by proving the hardware’s capability to meet stringent performance and reliability needs.
Next Steps Towards Commercial Deployment
With design completion secured, dorsaVi is advancing to tape-out and silicon fabrication. Validated chips will integrate into dorsaVi’s wearable sensor platforms, enabling on-device intelligence without external processing. Concurrently, the company plans to engage partners and customers across exoskeleton, defence, robotics, and industrial AI sectors to assess fit and commercial potential. This phase will be critical to translating technical validation into market traction.
CEO Mathew Regan emphasised the significance of this milestone, noting that the manufacturable architecture clears the path to physical silicon needed for performance validation and scaling. The company’s focus now shifts to fabrication and leveraging results to accelerate commercialisation.
Bottom Line?
The finalized RRAM-CMOS chip design positions dorsaVi to validate critical memory and compute innovations that could underpin next-generation ultra-edge AI devices, but silicon results and market engagement will be decisive for commercial success.
Questions in the middle?
- How will silicon test results influence dorsaVi’s 22-nm node development timeline?
- What partnerships or customer engagements will emerge from the upcoming market evaluation?
- How will dorsaVi’s write-and-verify and compute-in-memory features compare to competing edge AI memory solutions?