dorsaVi has moved from design to silicon manufacturing with the tape-out of its first 22-nm RRAM-CMOS validation chip, aiming to prove its advanced memory platform for AI and robotics applications.
- Tape-out marks transition from design to physical silicon
- Validation chip to test Compute-in-Memory and write-verify features
- Uses commercial CMOS wafers via TSMC for scalable manufacturing
- Targets AI, robotics, EVs, wearables with low-power memory
- Critical step toward commercial scaling of RRAM technology
Tape-Out Signals Physical Progress in RRAM Development
dorsaVi Limited (ASX:DVL) has taken a significant stride in its semiconductor ambitions by commencing the tape-out of its first 22-nanometre RRAM-CMOS validation chip. This process moves the project beyond design finalisation into the realm of physical silicon manufacturing, a crucial phase that tests the manufacturability of its advanced resistive RAM (RRAM) architecture under commercial foundry conditions.
The tape-out marks the preparation of the integrated circuit design package for fabrication, enabling wafer-level electrical testing and silicon validation. The chip is designed to generate critical data on RRAM-CMOS integration, memory array operation, and Compute-in-Memory (CIM) functionality, features that underpin dorsaVi’s vision for low-power, local intelligence in AI and robotics hardware.
Validation Chip to Benchmark Advanced Memory Features
Beyond being a manufacturing milestone, the validation chip serves as a testbed for several advanced memory capabilities. It integrates dedicated write-and-verify circuitry alongside CIM structures, allowing the same physical layer to store data and perform calculations locally. This addresses the traditional bottleneck of shuttling data between separate memory and processors, a major source of power drain and latency in edge devices.
By benchmarking these features on physical silicon, dorsaVi aims to validate resistance-state separation, sensing margins, and CIM readout behaviour, which are critical for deploying RRAM in real-world applications. This approach reflects the company’s broader strategy to embed validated silicon into platforms spanning exoskeletons, robotics, defence, and industrial AI, all of which demand local, non-volatile intelligence with minimal power consumption.
Commercial CMOS Front-End and Scalable Manufacturing
The validation chip’s manufacturing flow leverages commercial CMOS front-end wafers sourced through TSMC, with partner-led back-end-of-line (BEOL) integration of the RRAM stack. This staged silicon implementation pathway preserves flexibility for process learning and future node migration while ensuring compatibility with established foundry infrastructure.
This compatibility opens two potential pathways for dorsaVi: embedding RRAM technology directly into end devices or collaborating with foundries and fabless chip makers to develop specialised chips for targeted applications. Both routes aim to meet the soaring global demand for AI memory without requiring new manufacturing investments, enhancing the technology’s commercial viability.
Strategic Focus on Ultra-Edge AI and High-Value Markets
dorsaVi’s RRAM development aligns with its ultra-edge intelligence roadmap, which emphasises real-time AI-driven decisions at the point of sensing without cloud reliance. The validation chip supports this by enabling low-power, local processing essential for future sensing, robotics, exoskeletons, defence, medical wearables, and industrial AI hardware platforms.
CEO Mathew Regan described the tape-out as a “significant milestone” confirming the manufacturability of their architecture and providing the physical silicon needed for performance validation and refinement. The company is focused on executing the next testing phase to advance toward commercial scaling, underscoring the strategic importance of this milestone.
While the announcement stops short of specifying timelines for silicon test results or production scaling, the tape-out’s completion sets the stage for critical data generation that will shape dorsaVi’s RRAM integration and optimisation efforts moving forward.
Bottom Line?
The tape-out milestone brings dorsaVi’s RRAM technology from blueprint to silicon, setting up a crucial validation phase that could unlock scalable AI memory solutions for edge devices.
Questions in the middle?
- How will the forthcoming silicon test results influence dorsaVi’s commercial scaling timeline?
- What partnerships or collaborations might dorsaVi pursue to accelerate market adoption of its RRAM technology?
- How competitive is dorsaVi’s 22-nm RRAM platform compared to other emerging AI memory solutions?