Nanoveu’s 16nm Edge AI Chip Reaches First Silicon at TSMC

First Silicon Arrives From TSMC

Nanoveu Limited (ASX:NVU) has reached the most tangible milestone yet in its semiconductor program: the first packaged samples of EMASS’s 16nm ECS-DoT edge AI system-on-chip are now in the company’s hands. The chip has been fabricated by Taiwan Semiconductor Manufacturing Company on its 16nm FinFET process, turning a design completed late last year into physical silicon.

The program moved through GDS sign-off in December 2025, tape-out and entry into fabrication in January 2026, followed by wafer processing, dicing and packaging. That sequence was delivered as scheduled according to Nanoveu, but the commercial significance remains untested until the samples complete bring-up and characterisation.

A More Integrated ECS-DoT Platform

The 16nm device sits alongside the commercially available 22nm ECS-DoT as the second member of EMASS’s product family. The newer chip retains the RISC-V core, dual deep-learning accelerators and always-on design philosophy of the 22nm generation while adding a fully integrated Bluetooth Low Energy subsystem, expanded on-chip SRAM, a finer-grained power-management fabric and a dedicated object-detection engine.

It also introduces the first hardware floating-point unit in the ECS-DoT family, supporting FP16 and FP32 operations. Nanoveu says the additional integration could reduce the need for separate wireless hardware and help the chip handle larger neural networks, vision workloads and combined audio and sensor processing. Both devices are designed to share the same software stack, programming model and toolchain, allowing customers to move between nodes with minimal application-code changes.

Testing Now Replaces Design Estimates

EMASS will first power up the samples, establish communication and verify that the core subsystems function as designed. Testing will then cover the integrated radio’s transmit power, receive sensitivity and link performance, alongside AI accelerator throughput, inference latency, memory behaviour and the performance of the new floating-point unit.

Power measurements will examine active, idle and deep-sleep consumption, wake-up latency and energy per inference across representative vision, audio and sensor-fusion workloads. Nanoveu has not yet disclosed measured power, performance, yield, reliability or production timing. It intends to publish a summary of silicon results once characterisation is complete and then make engineering samples and evaluation boards available to selected customers and partners.

The Commercial Proof Point Is Still Ahead

The arrival of first silicon is a meaningful technical achievement, particularly because it is EMASS’s first ECS-DoT design at an advanced FinFET node. But it is not the same as a production win. The company still needs to show that the radio, memory, accelerators and power architecture work together within the targeted envelope, and that prospective customers see enough benefit to evaluate or adopt the device.

Nanoveu says it is also assessing smaller process nodes for future ECS-DoT generations. For now, the immediate catalyst is more prosaic and more important: the numbers that come back from the laboratory.