Chipforge clears independent FPGA test as Pathkey.AI advances toward commercial release

Pathkey.AI says an independent expert used its Chipforge platform to turn written specifications into working FPGA hardware without assistance from the company or manual code changes. The validation comes as Chipforge moves into pre-production customer work, but 88.5 million performance rights will also vest and the company’s benchmark comparisons remain internally generated.

  • Independent NTU evaluation produced working Digital Frequency Monitor and AES-128 FPGA designs
  • No Chipforge assistance or manual edits to generated code during the evaluation
  • Internal CVDP pass rates ranged from 67.0% to 74.3%, with comparisons subject to different testing methods
  • AMD Vivado and Altera Quartus workflows are complete, with Chipforge Studio targeted for Q1 2027
  • 74,999,997 Class A and 13,500,000 Class C performance rights satisfy vesting conditions
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Independent evaluation reaches working FPGA hardware

Pathkey.AI Ltd (ASX:PKY) has cleared a significant product hurdle for Chipforge: an independent expert took written hardware requirements through planning, code generation, simulation, debugging and deployment on a physical FPGA board, without help from the Chipforge team or manual edits to the generated code.

Chipforge Studio plan and design views, from an illustrative matrix multiplier example
Caption and image © Pathkey.AI Ltd. From “Independent Verification of Platform beyond design intent”, 4 Nov 2026.

Dr Smitha Kavallur Pisharath Gopi, a senior lecturer at Singapore’s Nanyang Technological University, tested the AMD Vivado workflow using a Digilent Nexys A7-100T board. The evaluation report records successful implementation of a Digital Frequency Monitor and AES-128 encryption over UART. Where changes were required, Dr Gopi described them to the platform, which then revised the design and reran the verification process.

Chipforge FPGA design workflow and the scope of the independent evaluation. Source: Chipforge
Caption and image © Pathkey.AI Ltd. From “Independent Verification of Platform beyond design intent”, 4 Nov 2026.

The result is narrower than a blanket certification of Chipforge. The evaluation covered agreed designs and the AMD Vivado workflow, rather than every commercial application. Altera Quartus integration is complete but was not included in the independent assessment.

Chipforge moves from acquisition to supported customer work

Since the June Chipforge acquisition, Pathkey says it has connected the FPGA workflow and built the software controls needed to support projects, including release management, performance monitoring and alerts. AMD Vivado and Altera Quartus are now supported, while Lattice and Microchip integrations are next on the development list.

Chipforge is already in pre-production release and supporting customer projects with engineering assistance. Its first commercial engagement, a ten-week proof-of-value programme, has completed its first phase; the next stage depends on the customer being ready to integrate the work into its mechanical solution. The contract was disclosed in the company’s first Chipforge customer contract, but today’s announcement does not provide a customer name or contract value.

Internal benchmark results lead published comparisons

Sets the Chipforge results beside published results for other systems on the same tasks
Caption and image © Pathkey.AI Ltd. From “Independent Verification of Platform beyond design intent”, 4 Nov 2026.

Pathkey’s internal testing covered 262 problems from NVIDIA’s public Comprehensive Verilog Design Problems benchmark. Chipforge recorded first-pass success rates of 67.0% for completing unfinished designs, 70.5% for creating designs from requirements, 70.9% for modifying existing designs and 74.3% for finding and correcting faults.

Those percentages were higher than published results cited for GPT-5, Claude 4 Sonnet and the MAGE research agent on the same task groups. The comparison needs careful handling: Chipforge’s results were first-pass, while the published figures counted a problem as solved if any of five attempts passed. The internal results have not been independently verified, and NVIDIA has not validated or endorsed them. Customer delivery, repeat use and engineering time saved will be more consequential tests than a simulation benchmark alone.

88.5 million performance rights satisfy vesting condition

The independent verification also triggers the vesting condition for 74,999,997 Class A Vendor Performance Rights and 13,500,000 Class C Incentive Performance Rights, a combined 88,499,997 rights issued under the Chipforge acquisition arrangements. The announcement does not state the resulting dilution as a percentage of securities on issue.

Pathkey is targeting a broader Chipforge Studio release in Q1 2027 while continuing supported FPGA projects. Longer-term work includes additional tool chains, customer-hosted deployment and further ASIC capability, although physical implementation and manufacturing handoff remain in development. The near-term question is whether the independently demonstrated workflow can convert into paid projects, accepted customer deliverables and repeat platform usage before the broader release arrives.

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Bottom Line?

The hardware demonstration strengthens Chipforge’s product case, but commercial traction, benchmark comparability and the effect of 88.5 million vesting rights remain the key tests ahead of the Q1 2027 release target.

Questions in the middle?

  • Will the first proof-of-value customer proceed to integration and generate further paid work?
  • Can Chipforge reproduce the demonstrated workflow across more designs, customers and FPGA tool chains?
  • What proportion of Pathkey’s securities on issue could the 88,499,997 vesting performance rights represent?

Sources

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