Adisyn Extends Graphene Patent Reach to Semiconductor Dielectrics

Adisyn Ltd (ASX:AI1) has secured a potentially important expansion of its graphene patent position: the United States Patent and Trademark Office has allowed an application covering direct deposition onto non-metallic surfaces, including the dielectric materials used around semiconductor wiring.

Patent Extends Protection Across the Interconnect Interface

The application, titled Method for Coating a Non-Metallic Surface with Graphene, is the company’s third allowed US patent application. Adisyn says its earlier allowed patents cover graphene deposition on metallic surfaces and the resulting metal-based interconnect products; this application addresses the other side of the barrier interface.

That distinction matters because a conventional semiconductor interconnect combines copper wiring with a barrier layer to prevent copper migration, while a surrounding dielectric layer provides insulation. The allowed claims cover a method for chemically binding graphene directly to that non-metallic surface using a molecular precursor, without damaging the underlying material.

Low-Temperature Process Includes Manufacturing Checks

The claimed process keeps the non-metallic surface below 400°C throughout deposition, consistent with Adisyn’s stated focus on low-temperature graphene growth for semiconductor manufacturing environments. The claims also incorporate quality verification during processing through at least one of Raman scattering, contact-angle measurement or fluorescence detection.

Adisyn says the technology could support graphene-based barrier layers along interconnect structures, including sidewalls between conducting wires and dielectric material. The company also points to possible relevance for chip miniaturisation, where shrinking wire dimensions make the space consumed by barrier and insulation layers increasingly important. Those are potential applications described by the company, rather than disclosed customer deployments or confirmed production outcomes.

Commercial Proof Remains the Next Test

Executive Chairman Kevin Crofton described the allowance as strengthening Adisyn’s intellectual property position as it works towards commercialisation. The announcement, however, contains no patent grant number, customer agreement, production commitment, revenue forecast or financial impact. Patent allowance is therefore a technology and legal milestone, not evidence that semiconductor manufacturers have adopted the process.

The immediate questions are whether the application proceeds to final issuance and whether the broader claims can translate into independent technical validation, industry partnerships or customer trials. Until those signals appear, the value of the expanded protection will remain tied to the still-unproven commercial pathway for Adisyn’s low-temperature graphene platform.